1. FIELD OF THE INVENTION
This invention relates to electronic accumulator circuits, and more particularly to a floating point accumulator integrated circuit.
2. BACKGROUND INFORMATION
In the prior art, electronic accumulators have typically been designed as circuit board level products, typically having a general architecture similar to that shown in FIG. 1. In such systems, floating point numbers were accumulated by comparing the exponents of two floating point numbers, aligning the binary point for both numbers, adding the two numbers, normalizing the result to a floating point number, and outputing the result, which is also fed back to the input for addition to the next number input to the circuit.
For an extremely high-speed computer system, it would be desirable to be able to accumulate floating point numbers in no more than one clock cycle of the system master clock. In the above-outlined prior art, it is either extremely expensive or virtually impossible to design an accumulator circuit that has such characteristics.
With advances in technology, circuitry from a circuit board level product can now be shrunken down onto a single integrated circuit chip. Reducing the size of the circuitry will inherently result in a faster processing speed. However, in some circumstances, such as in special purpose high speed graphics processing computers, ever higher speeds are desirable. Therefore, this invention presents a novel circuit design that obtains very high speed operation by using a pipelined architecture and feeding back the output of the addition circuit to the input of the accumulator circuit before normalization occurs. This results in a loss of some accuracy, but significantly speeds up the accumulation process, thus permitting a faster clock frequency and one clock cycle accumulation. In many instances, the loss of accuracy is negligible or tolerable, and the benefits of higher speed operation outweigh such loss.
Therefore, it is an object of the present invention to present a high speed, single clock cycle, pipelined floating point accumulator having a non-normalized feedback loop.